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an - 1161 application note one technology way ? p. o . box 9106 ? norwood, ma 02062 - 9106, u.s.a. ? tel: 781.329.4700 ? fax: 781.461.3113 ? www.analog.com emc - c ompliant rs - 485 communication networks b y james scanlon rev. 0 | page 1 of 16 introduction in real industrial and instrumentation (i&i) applications , rs - 485 communication links must work in harsh electromagnetic environmen ts. large transient voltages caused by lightning strikes, electrostatic discharge , and other electro magnetic phenomenon ca n cause damage to communication ports. these data ports must meet certain electromagnetic compatibility (emc) regulations to ensure th at they can survive in their final installation environments . within these requirements, there are three transient immunity standards : electrostatic discharge, electrical fast transients , and surge . leaving emc considerations to the end of the design cycle leads to penalties , such as engin eering budget and schedule over runs. many emc problems are not simple or obvious and must be considered at the start of product design. this application note descr ibes each of these transients, present s the design solution methodology , and demonstrate s three different emc - compliant solu tions for three different cost/ protection levels for rs - 485 communication ports. these different solutions are illustrated in figure 1 . analog devices , inc., and bourns , inc., have partnered to extend their offering of system oriented solutions by co - developing th e industrys first emc - c ompliant r s - 485 interface customer design tool . this tool provid es , up to and including , level 4 protection levels for iec 61000- 4 - 2 esd, iec 61000 - 4 - 4 eft , and iec 61000 - 4 - 5 surge . it gives designers the design options depending up on the level of protection r equired and available budgets. these design tools allow designers to reduce risk of project slippage due to emc problems by considering them at the start of the design cycle. figure 1. three emc com pliant solutions 10904-100 di de ro re v cc adm3485e b a tvs protection scheme 1. tvs di de ro re v cc adm3485e b a tvs tbu tisp protection scheme 2. tvs/tbu/tisp gdt di de ro re v cc adm3485e protection scheme 3. tvs/tbu/gdt b a tvs tbu
an- 1161 application note rev. 0 | page 2 of 16 table of contents introduction ...................................................................................... 1 revision history ............................................................................... 2 rs - 485 standard ............................................................................... 3 electromagneti c compatibility ....................................................... 4 electrostatic discharge ................................................................ 4 electrical fast transients ............................................................. 5 surge ............................................................................................... 7 pass/fail criteria .......................................................................... 8 theory of protection .........................................................................9 rs - 485 transient suppression networks .................................... 10 protection scheme 1 .................................................................. 10 protection scheme 2 .................................................................. 11 protection scheme 3 .................................................................. 12 conclusion ....................................................................................... 13 references ........................................................................................ 14 revision history 2 /13 rev ision 0: initial version
application note an- 1161 rev. 0 | page 3 of 16 rs- 485 s tandard i&i applications require the transmission of data between multiple systems , often over very long distances. the rs - 485 bus standard is one of the most widely used physical layer bus designs in i&i applications. applications for rs - 485 include process control networks; industrial auto mation; remote terminals; building automation, such as heating, ventilation, and air conditioning (hvac); security systems; motor control; and motion control. the key features of rs - 485 that make it ideal for use in i&i communications applications are ? long distance links up to 4000 feet. ? bidirectional communications possible over a single pair of twisted cables. ? differential transmission increases noise immunity and decreases noise emissions. ? multiple drivers and receivers can be connected on the same bus. ? wide common - mode range ( ?7 v to +12 v) allows for differences in ground potential between the driver and receiver. ? tia/eia - 485- a allow for data rates of tens of mbps. tia/eia - 485- a, the telecommunication industrys most widely used transmission line standard, describes the physical layer of the rs - 485 interface and is normally used with a higher level protocol, such as p rofibus , interbus, modbus, or bacnet. this allows for robust dat a transmission over relatively long distances. in real applications, however , lightning strikes, power induction and direct contact, power source fluctuations, inductive switching, and electrostatic discharge can cause damage to rs - 485 tran s ceivers by ge nerating large transient voltages. designers must ensure that equipment does not just work in ideal conditions , but that it must also work in real world situations. in order to ensure that these designs can survive in electrically harsh environments, vario us government agencies and regulatory bodies have imposed emc regulations. compliance with these regulations assures the end user that designs will operate as desired in these harsh electromagnetic environments .
an- 1161 application note rev. 0 | page 4 of 16 electroma gnetic compatibility emc is the ability of an electronic system to function satis - factorily in its intended electromagnetic environment without introducing intolerable electromagnetic disturbances to that environment. an electr omagnetic environment is composed of both radiated and conducted energy. therefore, emc has two aspects , emission and susceptibility. emission is the unwanted generation of electromagnetic energy by a product. it is often desirable to control emission in order to crea te an electromagnetically - compatible environment. susceptibility is a measure of the ability of electronic products to tolerate the influence of electromagnetic energy radiated or conducted from other electronic products or electromagnetic inf luences. i mmunity is the opposite of susceptibility . equipment that has high susceptibility has low immunity. the international electrotechnical commission (iec) is the worlds leading organization that prepares and publishes international standards for all electrical, electronic , and related technologies. since 1996, all electronic equipment sold to or within the european c ommunity must meet emc levels as defined in specification iec 61000 - 4 - x . the iec 61000 specifications define the set of emc immunity requirements that apply to electrical and electronic equipment intended for use in residential, commercial , and light industrial environments. within this set of specifications, there are three types of high voltage transients that electronic designers ne ed t o be concerned about for data communication lines . these are ? iec 61000 - 4 - 2 electrostatic discharge (esd) ? iec 61000 - 4 - 4 electrical fast transients (eft) ? iec 61000 - 4 - 5 surge immunity this application note deals with increasing the protection level of rs - 485 ports to protect against the these three main emc transients. each of these specifications defines a test method to assess the immunity of electronic and electrical equipment against the defined phenomeno n. the following section s provide a summary of each of these tests. electrostatic discha rge esd is the sudden transfer of electrostatic charge between bodies at different potentials caused by near contact o r induced by an electric field. it has the charac teristics of high current in a short time period. an object can become charged due to a number of mechanisms. a charge can occur by simple contact with another charged object. it can also occur as a re sult of triboelectric charging , which is the generatio n of static electricity caused by rubbing two substances together. alternatively, an object can be charged as a result of induction charging. in this case , there is no physical contact with the charged object yet charging can occur if it is within the elec tric field of the charged object. the primary purpose of the iec 61000- 4 - 2 test is to determine the immunity of systems to external esd events outside the system during operation . iec 61000 - 4 - 2 specifies testing using two coupling methods, contact discharg e and air - gap discharge. contact discharge implies the discharge gun is placed in direct connection with the unit under tested. air gap discharge uses a higher test voltage , but does not make direct contact with the unit under test. during air discharge testing, the charged electrode of the discharge gun is moved toward the unit under test until a discharge occurs as an arc across the air gap. the discharge gun does not make direct contact with the unit under test. a number of factor s affect the results and repeatability of the air discharge test, including humidity, temperature, barometric pressure, distance , and rate of approach to the unit under test. this method is a better representation of an actual esd event, but is not as repe atable. therefore, contact discharge is the preferred test method. iec 61000- 4 - 2 specifies voltage test levels for different environ - mental conditions along with a current waveform. table 1 shows the relationship between the environment and the test voltage. the test levels should be selected in accordance with the most realistic installation and environment conditions the fin al product will be subjected to. l evel 1 is the least severe and l evel 4 the most severe. level 1 and level 2 are for products installed in controlled environ - ments that h ave antistatic material. level 3 and level 4 are for products installed in more seve re environments where esd events with higher voltages are more common. figure 2 shows the 8 kv contact discharge current waveform as described in the specification. some of the key waveform parameters to note are fast rise times of less than 1 ns and short puls e widths of approximately 60 ns . this equates to a pulse with total energy in the range of ten s of mj. the test is performed with single discharges. the test p oint is subjected to at least 10 positive and 10 negative discharges. a 1 s interval between discharges is recommended.
application note an- 1161 rev. 0 | page 5 of 16 figure 2. iec 61000 - 4- 2 esd waveform (8 kv) table 1 . iec 61000 - 4 - 2 test levels and installation classes level /class relative humidity as low as % antistatic material synthetic material contact discharge test voltage (kv) air discharge test voltage (kv) 1 35 x 2 2 2 10 x 4 4 3 50 x 6 8 4 10 x 8 15 electrical fast tran sients electrical fast transient testing involves coupling a number of extremely fast transient impulses onto the signal lines to represent transient disturbances associated with e xternal switchi ng circuits that are capacitiv e l y coupled onto the communication ports . this may include relay and switch contact bounce or transients originating from the switching o f inductive or capacitive loads all of which are common in industrial env ironments. the eft test defined in iec 61000 - 4 - 4 attempts to simulate the interference resulting from these types of events. figure 3 shows the eft 50 load waveform. the eft waveform is described in terms of a voltage across 50 impedance from a generator with 50 output impedance. the output waveform consists of a 15 ms burst 5 khz high voltage transients repeated at 300 ms intervals. each individual pulse has a rise time of 5 ns and pulse duration of 50 ns, measured between the 50% point on the rising and falling edges of the waveform. similar to the esd transient, th e eft pulse has the characteristics of fast rise time and short pulse width. the total energy in a single pulse is similar to that of an esd pulse . voltages applied to the data ports can be as high as 2 kv. these fast burst transients are coupled onto the communication lines using a capacitive clamp. the eft is capacitiv e ly coupled onto the communication lines by the clamp rather than direct contact. this also reduces the loading caused by the low output impedance of the eft generator. the coupling capacita nce between the clamp and cable depends on cable diameter, shielding, and insulation on the cable. iec 61000 - 4 - 4 specifies voltage test levels for different environ - mental conditions. table 2 shows the test voltage and pulse repetition rates for the different test levels. the test levels should be selected according to the most realistic installation and environment al conditions t he final product will be subected to. traditionally , 5 khz repetition rates are used, however this rate is generally dependent on the end manufacturers specification. ? level 1 well protected ? level 2 protected environments ? level 3 typical industrial envir onment ? level 4 severe industrial environment table 2 . iec 61000 - 4 - 4 test levels data port test voltages and repetition rates level voltage p eak (kv) repetition rate (khz) 1 0.25 5 or 100 2 0.5 5 or 100 3 1 5 or 100 4 2 5 or 100 i peak 30a 90% 16a 8a i 30ns i 60ns 10% t r = 0.7ns to 1ns 30 ns 60 ns t 10904-001
an- 1161 application note rev. 0 | page 6 of 16 figure 3. iec 61000 - 4- 4 eft 50 ? waveform t (ns) t (ms) t (ms) t r t r = 5ns 30% t d = 50ns 30% t d repetitive bursts v peak single pulse burst of pulses 100% v peak 90% 50% 10% 15ms 300ms 10904-002
application note an- 1161 rev. 0 | page 7 of 16 surge surge t ransients are caused by overvoltages from switching or lightning transients. switching transients can result from power system switching, load changes in power distribution systems , or various system faults , such as short circuits and arching faults to the grounding system of the installatio n. lightning transients can be a result of high currents and voltages injected into the circuit from nearby lightning strikes. iec 61000- 4 - 5 defines waveforms, test methods , and test levels for evaluating the immunity of electrical and electronic equipment when subjected to these surges. the waveforms are specified as the outputs of a wave form generator in terms of open - circuit voltage and short - circuit current. two waveforms are described. the 10 s /700 s combination waveform is used to test ports intende d for connection to symmetrical communication lines, for example telephone exchange lines. the 1.2 s /50 s combination waveform generator is used in all other cases, in particular short distance signal connections. for rs - 485 ports , the 1.2 s /50 s waveform is predominantly used. the waveform generator has an effective output impedance of 2 ?, thus the surge transient has high currents associated with it. figure 4 shows the 1.2 s /50 s s urge transient waveform. esd and eft have similar rise times, pulse widths , and energy levels. with surge , the rise time of the pulse is 1.25 s and the pulse width is 50 s. the surge pulse energy can have energy levels that are three to four orders of magnitude larger than the energy in an esd or eft pulse. therefore, the surge transient is considered the most sever e of the emc transient specs. due to the similariti es between esd and eft , the design of the circuit protection can be similar, however , due to its high energy , surge must be dealt with differently. this i s one of the main issues in developing protection circuitry that improves the immunity of data ports t o all three transients while remaining cost effective. figure 4 . iec 61000 - 4- 5 surge 1.2 s/50 s waveform 10904-003 v peak 90% 100% 50% 10% 30% max t 2 t (s) t 1 t 1 = 1.2s 30% t 2 = 50s 20%
an- 1161 application note rev. 0 | page 8 of 16 resistors couple the surge transient onto the communication line. figure 5 shows the coupling network for a half - duplex r s - 485 device. the total parallel sum of the resistance is 40 ?. for the half - duplex device , each resistor is 80 . figure 5. surge coupling network for a half - duplex rs - 485 device table 3 . iec 61000 - 4 -5 t est levels level pen - circit test voltae 1 0.5 kv 2 1 kv 3 2 kv 4 4 kv x special the test levels as defined in the iec 61000- 4 - 5 are shown in table 3 . leve l x can be above, below , or in between the other levels. this is usually specified in the product standard. the test levels should be selected according to the inst allation conditions. there are six classes of installations defined in the spec i fi cation. ? class 0 ( well pr otected electrical environment ) ? class 1 ( partially p rotected electrical environment ) ? class 2 ( e lectrical en vironment where cables are well separated, even at short runs ) ? class 3 ( e lectrical environment where power and signal cables run in parallel ) ? class 4 ( e lectrical environment where the intercom - nections are running as outdoor cables along with power cables, and cables are used for both ele ctronic and electrical circuit s ) ? class 5 ( e lectrical environment for electronic equipment connected to telecommunication cables an d overhead power lines in a non densely populated environment ) ? class x ( s pecial conditions specified in the product specifications ) class 0 has no surge transient treat associated with it. class 5 has the most severe transient stress level. a summary of the installation class es and the surge voltage for each class is shown in table 4 . table 4 shows the test voltages associated with each class for line to ground coupling for symmetric and unsymmetrica l lines. it is important that the final environment class is know n to ensure the product is immune to the threat level. table 4 . iec 61000 - 4 -5 installation classes installation class nsm etrical lines test levels sm etrical lines test levels 0 na na 1 0.5 kv 0.5 kv 2 1 kv 1 kv 3 2 kv 2 kv 4 4 kv 2 kv 5 4 kv 4 kv during the s urge test , five positive , and five negative pulses are applied to the data ports with a maximum time interval of 1 minute between each pulse. the standard states that the device should be set up in normal operating conditions for the duration of the test . pass/fail c riteria when transients are applied to the system under test , the results are categorized into four pass/fail criteria. following is a list of the pass/fail criteria giving examples how each might relate to an rs - 485 transceiver: a. normal performance; n o bit errors would occur during or after the transient is applied. b. temporary loss of function or temporary degradation of performance not requiring an operator; b it errors might occur during and for a limited time after the transient is applied. c. temporary loss of function or temporary degradation of performance requiring an operator; a latch - up event may occur that could be removed after a power on reset with no permanent or degradation to the device. d. loss of function with permanent damage to equipment. the device fails the test. criteria a is the most desirable and c rite ria d is unacceptable. permanen t damage results in system down time and the expense of repair and replacement. for mission critical systems, criteria b and c riteria c are also unacceptable because the system must operate without errors during transient even ts. 10904-004 di de ro re v cc adm3485e b a protection components 80 cdn 80
application note an- 1161 rev. 0 | page 9 of 16 theory of p rotection there are three main ways to prevent emc problems. ? suppress the transient at source . ? make the coupling path as inefficient as possible . ? make the device less susceptible to the transient. often it is not possible to remove the source of the transient, for example , it is not possible to control where lightning strikes occur. reducing the possibility of coupling is often beyond the manufacturers control wh en the final product is installed. in order to ensure the product is emc compatible , it is often necessary for the manufacturer to add protection to the data ports to make the product less susceptible to these transients. when designing protection circuitr y to protect against transients, consider the following: ? it must prevent or limit damage caused by the transient and allow the system to return to normal operation with minimal impact on performance. ? the protection scheme should be robust enough to deal w ith the type of transients and voltage levels the system would be subjected to in the field. ? the length of time associated with the transient is an important factor. for long transients , heating effects can cause certain protection schemes to fail. ? under normal operation conditions, the protection circuitry should not interfere with the system operation. ? if the protection circuitry fails during overstress, it should fail in a way that protect s the system. there are two main types of protection schemes used to p rotect against transients. over current protection is used to limit peak current and over voltage protection is used to limit peak voltages. there is a broad range of overcurrent and overvoltage protection technologies and components available in t he market, each one with its own advanta ges and disadvantages . developing protection for a system usually requires the use of both overvoltage and overcurrent protection devices. figure 6 shows a typical design for a protection scheme. the design can be characterized by having primary and secondary protection. primary protection diverts most of the transient energy away from the system and is typically located at the interface between the system and the environment. it is designed to remove the majority of the energy by diverting the transient to gro und. the function of the s econdary protection is to protect various parts of the system from any transient voltages and currents let through by the primary protection. the secondary protection is usually designed to be more specific to the part of the sys tem it is protecting. it is optimized to ensure that it protects against these residual transient s while allowing normal operation of these sensitive parts of the system. it is essential that both the primary and secondary designs are specified to work tog ether in conjunction with the system input/output to minimiz e the stress on the protected circuit. these designs typically include a coordinating element , such as a resistance or a nonlinear overcurrent protection device , between the primary and secondar y protection devices to ensure that coordination occurs. figure 6. protec tion scheme block diagram overcurrent protector overvoltage protector system harsh electromagnetic environment overvoltage protector secondary protection primary protection 10904-005
an- 1161 application note rev. 0 | page 10 of 16 rs- 485 transient suppre ssion networks emc transient events vary in time, s o the dynamic performance and the matching of the dynamic characteristics of the protection components with the input/output stage of the protected device l eads to successful emc design. component data sheets generally only contain dc data, which is of limited value given that the dynamic breakdowns and i/v characteristics can be quite different from the dc values. careful design, characterization , and an understanding of the dynamic performance of the i nput/output stage of the protected device and the protection components is required to ensure that the circuit meets emc standards. this application note presents three di fferent fully characterized emc - compliant solutions. each solution was certified by a n independent external emc compliance test house, and each provides different cost/protection levels for the analog devices adm3485e 3.3 v rs - 485 tr ansceiver with enhanced esd protection using a selection of bourns external circuit protection components. the bourns external circuit protection components used consist of transient voltage suppressors ( cdsot23 - sm712 ), transient blocking unit s ( tbu - ca065 - 200- wh ), thyristor surge protectors ( tisp4240m3bjr - s ) , and gas discharge tubes ( 2038- 15- sm - rplf ). each solution was characterized to ensure the dynamic i/v performance of the protection components protect the dynamic i/v characteristics of the adm3485e rs - 485 bus pins. it is the interaction between the input/output stage of the adm3485e and the external protection components that f unction together to protect against the transient events. protection scheme 1 the eft and esd transient have similar energy levels, while the surge waveform has energy levels three to four magnitudes greater. protecting against esd and eft is accomplished in a similar manner, but p rotecting against high levels of surge requires solutions that are more complex . the first solution described protects up to level 4 esd and eft and level 2 surge. the 1.2 s /50 s waveform is used in all surge testing described in this application note. t his solution uses the bourns cdsot23 - sm712 transient voltage suppressor (tvs) array which consists of two bidirectional tvs diodes as il lustrated in figure 7 . table 5 shows the voltage levels protected against for esd, eft , and surge transients. figure 7. protection scheme 1 tvs tale 5 . s cheme 1 protection levels esd ( - 4 - 2) e f t ( - 4 - 4) surge ( - 4 - 5) level volt age (contact/air) level volt age level volt age 4 8 kv/15 kv 4 2 kv 2 1 kv a tvs is a silicon - based device. under normal operating conditions, the tvs has high impedance to ground; ideally , it is an open circuit. the protection is accomplished by clamping the overvoltage from a transient to a voltage limit. this is done by the low impedance avalanche breakdown of a pn junction. when a transient voltage larger than the breakdown voltage of the tvs is generated, the tvs clamps the transient to a predetermined level that is less than the breakdown voltage of the devices that it is protecting. the transients are clamped instantaneously (< 1 ns) and the transient current is diverted away from the protected device to ground. it i s important to ensur e that the breakdown voltage of the tvs is outside the normal operating range of the pins protected. as demonstrated in figure 8 , t he unique feature of the cdsot23 - sm712 is that it has asymmetrical breakdown vol tages of +13.3 v and C 7.5 v to match the tran sce iver common - mode range of +12 v to C 7 v , therefore providing optimum protection while minimizing overvoltage stresses on the adm3485e rs - 485 transce iver. figure 8. cdsot23 - sm712 i/v characteristic 10904-006 di de ro re v cc adm3485e b a tvs 10904-007 i v v br = 13.3v v br = 7.5v
application note an- 1161 rev. 0 | page 11 of 16 protection s cheme 2 the previous solution protects up to level 4 esd and eft, but only to level 2 surge. to improve the surge protection level, the protection circuitry gets more complex. the protection solution presented in this section protect s up to level 4 surge. the cd sot23 - sm712 is specifically designed for rs - 485 data ports . the next two solution s build on the cdsot23 - sm712 to provide higher levels of circuit protection. in this solution, the cdsot23 - sm712 provides secondar y protection while the tisp4240m3bjr - s provides the primary protection. coordination between the primary and secondary protection devices , and overcurrent protection is accomplished using the tbu - ca065 - 200- wh . table 6 shows the voltage levels protected against for esd, eft , and surge transie nts with th is solution. figure 9 shows a representation of the complete solution . figure 9. protection scheme 2 tvs/tbu/ tisp tale 6 . scheme 2 protection levels esd ( - 4 - 2) e f t ( - 4 - 4) surge ( - 4 - 5) level volt age (contact/air) level volt age level volt age 4 8 kv/15 kv 4 2 kv 4 4 kv when a transient is applied to the protection circuit, the tvs breaks down providing a low impedance path to ground to protect the device. with large voltages and currents, there is a need to protect the tvs and limit the current through it. this is done using a transient blocking unit (tbu), which is an active high speed overcu rrent protection element. the tbu in this design is the bourns tbu - ca065 - 200- wh . a tbu blocks current rather than shunting it to ground. as a series component, it reacts to current through the device rather than the voltage across the interface. a tbu is a high speed overcurrent protection component with a preset current limit and a high voltage withstand capability. when an overcurrent occurs and the tvs breaks down due to the transient event, the current in the tbu will rise to the current limiting level set by the device. at this point, the tbu disconnects the protected circuitry from the surge in less than 1 s. during the remainder of the transient, the tbu remains in the protected blocking state, with very low current (<1 ma) passing through the prot ected circuit. under normal operating conditions, the tbu exhibits low impedance, so it has minimal impact on normal circuit operation. in blocking mode, it has very high impedance to block transient energy. after the transient event, the tbu automatically resets to its low imped - ance state and reinstates the system allowing resumption of normal operation. like all overcurrent protection technologies, the tbu has a maximum breakdown voltage, so a primary protection device must clamp the voltage and redirec t t he transient energy to ground. this is commonly done using technologies , such as gas discharge tubes or solid - state thyristors , such as the totally integrated surge protector (tisp). the tisp acts as a primary protection device. when its predefined prot ection voltage is exceeded, it provides a crowbar low impedance path to ground, thus diverting the majority of the transient energy away from the system and other protection devices. the nonlinear voltage - current characteristic of the tisp limits overvolt age by diverting the resultant current. as a thyristor, a tisp has a discontinuous voltage - current characteristic caused by the switching action between high and low voltage regions. figure 10 shows the voltage - current characteristic of the device. before the tisp device switches into a low voltage state , with low impedance to ground to shunt the transient energy , a clamping action is caused by the avalanche breakdown region. in limiting an overvoltage, the protected circuitry will be exposed to a high voltage for the brief time period that the tisp device is in the breakdown region , before it switch es into a low voltage protected on - state . the tbu will prote ct the down - stream circuitry from high currents resulting from this high voltage. when the diverted current falls below a critical value, the tisp device automatically resets allowing normal system operation to resume . as described, all three components work together in conjunction with the system input/output to protect the system from high voltage and current transients. 10904-008 di de ro re v cc adm3485e b a tvs tbu tisp
an- 1161 application note rev. 0 | page 12 of 16 figure 10 . tisp switching characteristic and voltage limiting waveshape protection scheme 3 protection levels above level 4 surge are often required. the protection scheme shown in figure 11 protect s rs - 485 ports up to and including 6 kv surge transients. it operates in a similar fashion to p rotection s cheme 2 ; however, in this circuit, a gas discharge tube (gdt) is used in place of the tisp to protect the tbu, which is , in turn , protecting the tvs, the secondary protection device. the gdt will provide protection to higher overvoltage and overcurrent stress than the tisp described in the protection scheme 2 section . the gdt for this protectio n scheme is the bourns 2038 - 15- sm - r p l f. t h e tisp is rated at 220 a v s. the gdt rating of 5 ka per conductor. table 7 summarizes the protection levels provided by this design. figure 11 . protection scheme 3 tvs/tbu /gdt tale 7 . s cheme 3 protection levels esd ( - 4 - 2) e f t ( - 4 - 4) surge ( - 4 - 5) level volt age (contact/air) level volt age level volt age 4 8 kv/15 kv 4 2 kv x 6 kv predominately used as a primary protection device, a gdt provides a low impedance path to ground to protect against overvoltage transients. when a transient voltage reaches the gdt spark - over voltage, the gdt switches from a high impedance off - state to arc mode. in arc mode, the gdt becomes a virtual short, providing a crowbar current path to ground and diverting the transient current away from the protected device. figure 12 shows the typical characteristics of a gdt. when the voltage across a gdt increases, the gas in the tube starts to ionize due to the charge developed across it. this is known as the glow region. in this region, the increased current flow create s an avalanche effect that transition s the gdt into a virtual short circuit, allowing current to pass throu gh the device. during the short - circuit event, the voltage developed across the device is known as the arc voltage. the transition time between the glow a nd arc region is highly dependent on the physical characteristics of the device. figure 12 . gdt characteristic waveform 10904-009 v i spd current system rated voltage current at rated voltage breakdown region voltage protection level overvoltage system rated voltage voltage protection level tisp gdt 10904-010 di de ro re v cc adm3485e b a tvs tbu arc region impulse sparkover voltage (typical 500v) time voltage glow region arc voltage (typical 10v to 20v) 10904-0 1 1
application note an- 1161 rev. 0 | page 13 of 16 conclusion this a pplication note describ e s the three iec standards of interest that deal with transient immunity. in real industrial applications, rs - 485 communication ports subjected to these transients can be damaged. emc problems discovered late in a product design cycle may require expensive redesign and can of ten lead to schedule overruns. emc problems should therefore be considered at the start of the design cycle and not at a later stage where it may be too late to achieve the desired emc performan ce. the key challenge in designing emc - compliant solutions for rs - 485 networks is matching the dynamic performance of the external protection components with the dynamic performance of the i nput/output structure of the rs - 485 device . this application note demonstrated three different emc compliant solutions for rs - 485 communication ports, giving the designer options depending on the level of protection required. the e va l - cn0313 - sdp z is industrys first emc - compliant rs - 485 custom er design tool, providing up to level 4 protection levels for esd, eft , and surge. the protection levels offered by the different protection schemes are summarized in table 7 . while these design tools do not replace the due diligence or qualification required at the system level, they allow the designer to reduce the risk of project slippage due to emc problems a t the start of the design cycle, thus reducing design time and time to market. for more information , visit: www.analog.com/rs485emc . table 4. three adm3485e emc - compliant s chemes esd ( - 4 - 2) eft ( - 4 - 4) surge ( - 4 - 5) protection scheme level volt age (contact/air) level voltage level voltage 1. tvs 4 8 kv/15 kv 4 2 kv 2 1 kv 2. tvs/tbu/tisp 4 8 kv/15 kv 4 2 kv 4 4 kv 3. tvs/tbu/ gdt 4 8 kv/15 kv 4 2 kv x 6 kv
an- 1161 application note rev. 0 | page 14 of 16 references more information regarding interface and isolation products is listed in this section (also see the analog devices website ) . see the bou rns website for information on parts mentioned in this document as well as for the first principles document and the bournes telecom protection guide . adm3485e data sheet. analog devices, inc . electromagnetic compatibility (emc) part 4 - 2: testing and measurement techniques electrostatic discharge immunity test (iec 61000 - 4 - 2:2008 (ed.2.0)). electromagnetic compatibility (emc) part 4 - 4: testing and measurement techniques electrical fast transient/burst immunity test (iec 61000 - 4 - 4:2012 (ed3.0)). electromagnetic compatibility (emc) part 4 - 5: testing and measurement techniques surge immunity test (iec 61000- 4 - 5:2005 (ed2.0)). e va l - cn0313 - sdpz . www.analog.com/rs485emc . marais, hein. rs - 485 /rs - 422 circuit implementation guide . application note an - 960 . analog devices, inc.
application note an- 1161 rev. 0 | page 15 of 16 notes
an- 1161 application note rev. 0 | page 16 of 16 notes ? 2013 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. an10904 - 0 - 2/13(0)

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